Module IES-2005:
Digital Circuits 2

Module Facts

Run by School of Computer Science and Electronic Engineering

10 Credits or 5 ECTS Credits

Semester 1

Organiser: Dr Iestyn Pierce

Overall aims and purpose

To build upon the basic knowledge of digital circuits gained from IME1006 and to prepare the students for digital signal processing and FPGA-based project work.

Course content

Review of Boolean algebra, Karnaugh maps, combinational circuits, programmable logic. CMOS logic.

Synchronous Finite State Machines. Analysis and synthesis of ‘Moore’ and ‘Mealy’ synchronous circuits. Partition Minimisation, State Assignment.

Asynchronous sequential circuits, analysis, avoiding races and hazards. Synthesis methods. Partition Minimisation for Asynchronous Circuits. State Merge.

Circuits for addition, subtraction and multiplication, including speed-up techniques. Carry-look ahead, array multipliers. Multi-operand addition. Wallace and Dadda Trees.

The problems of testing complex digital circuits. Path sensitisation.

Learning outcomes mapped to assessment criteria

  threshold

40%

good

60%

excellent

70%

Understand the principles of synchronous digital circuit design.

Can design and analyse basic synchronous circuits. Knows difference between a Moore and a Mealy FSM. Can draw simple CMOS gate schematics. Can state the definition of equivalent states. Can design and analyse complex synchronous circuits with some guidance. Can explain the operation of all basic CMOS logic structures. Can perform partition minimisation correctly. Can design complex synchronous circuits to meet specification with minimal guidance. Shows good judgement in evaluating designs.

Understand the principles of asynchronous digital circuit design.

Can use Karnaugh maps and Boolean algebra to design and analyse basic asynchronous circuits. Can describe what is meant by a hazard in an asynchronous circuit. Can state the conditions of state compatibility. Can design and analyse complex asynchronous circuits with some guidance. Understands the risk of hazards and can design hazard-free asynchronous circuits. Can perform partition and merge correctly. Can design complex asynchronous circuits to meet specification with minimal guidance. Shows good judgement in evaluating designs.

Understand the structure and operation of common circuits used for computer arithmetic.

Can describe and explain the operation of circuits for addition and subtraction. Can describe and explain the operation of standard circuits for multiplication. Can explain the principles of carry-look ahead adders. Can draw a Wallace tree for a given problem. Can derive Wallace and Dadda trees for a problem, and compare them.

Show a basic knowledge of the common approaches to the testing of digital circuits.

Can state the algorithm for path sensitisation testing for stuck-at states in simple circuits. Can state the expression for the number of k-node stuck-at faults in a circuit. Shows sound knowledge of path sensitisation testing. Can derive the expression for the number of k-node stuck-at faults in a circuit. Can sensibly evaluate the resulting set of test vectors. Shows understanding of the limitations of test methods.

Assessment Methods

Type Name Description Weight
Exam 100

Teaching and Learning Strategy

Hours
Private study

Worked examples, design problems, attempting tutorial questions, completing past exam papers, revision.

76
Lecture

2 x 1 hour lectures per week for 12 weeks 4 x 1 hour tutorials delivered in lecture slots

24

Pre- and Co-requisite Modules

Courses including this module